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CH7001C
CHRONTEL
VGA to NTSC/PAL Encoder
Features
* Enhanced bandwidth and signal-to-noise ratio for higher video performance * Integrated triple video rate 8-bit analog to digital converters for input RGB * 3-line digital vertical filtering with pinprogrammable characteristics for optimum antiflicker and resolution * On-chip phase-locked loop generates sampling clock from VGA horizontal sync * Enhanced power management for selective circuit power-down * Simultaneous composite/S-video output * Horizontal and vertical position control * Pin-programmable underscan/overscan mode * On-chip reference generation and loop filter * CMOS technology in 44-pin PLCC * 5V supply
Description
Chrontel's CH7001C VGA to NTSC/PAL encoder is a stand-alone integrated circuit that converts analog VGA inputs directly into 525-line (M) NTSC or 625-line (B, D, G, H, I) PAL composite video and S-video outputs. This circuit integrates a digital NTSC/PAL encoder with 8-bit ADC and DAC interfaces, a 3-line vertical filter and low-jitter phase-locked loop to create outstanding quality video with 24-bits-per-pixel processing throughout the entire signal path. A high level of integration and performance makes the CH7001C ideal for a variety of stand-alone and systemlevel integration solutions, including notebook computers and PC add-on graphics cards.
HORIZONTAL, VERTICAL POSITION CONTROL
STROBE
CLKOUT CLKEN*
NTSC/PAL*
PD[1:0]
VDD
DVDD AVDD
RSET
VREF1
VREF2
RSET
VREF
UNDERSCAN
BLANKING H,V SYNC GENERATOR
MS[1:0]
Y FILTER
M U X
DAC
Y
R
ADC ADC ADC
V FILTER M U X
VERTICAL FILTER SCAN-RATE CONVERTER COLOR SPACE CONVERTER
U FILTER M U X
DAC
CVBS
G
X
DAC
C
B
X
SIN + COSINE GENERATOR
H
SYSTEM CLOCKS
BLANKING COLOR-BURST CONTROL
PLL
V
OSC
Figure 1: Functional Block Diagram
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1
CHRONTEL
CH7001C
STROBE
VREF1 41
AGND
AGND
AGND
6
5
4
3
2
1
44
43
42
CLKEN* CLKOUT DVDD DGND MS0 MS1 DVDD DGND XI XO/FIN PDI
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
40 39 38 37 36
AGND
AVDD
AVDD
G
R
B
VREF2 AVDD PD0 TEST* H V UNDERSCAN DVDD DGND NTSC/PAL* RIGHT
CHRONTEL CH7001C
35 34 33 32 31 30 29
VDD
GND
C
GND
VDD
DOWN
Y
CVBS
RSET
UP
Figure 2: 44-pin PLCC
2
LEFT
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CHRONTEL
Table 1 * Pin Description
Pin Type Symbol Description
CH7001C
1, 5, 40, 42
Power
AGND
Analog ground These pins provide the ground reference for the analog section of CH7001C, and MUST be connected to the system ground to prevent latchup. Please refer to Application Note AN-11 for information on proper supply decoupling. VGA Inputs 1 These pins should be terminated with 75 resistors and isolated from switching digital signals and video output pins. Analog Supply Voltage These pins supply the 5V power to the analog section of the CH7001C. For information on proper supply decoupling, please refer to Application Note AN-11. Strobe Input (active high, internal pull-up) A logical HIGH input to this pin keeps chip mode pins (CLKEN*, UNDERSCAN, MS[1:0], UP, DOWN, LEFT, and RIGHT) active. These input signals are internally sampled on the high-to-low transition of the STROBE signal. This allows the chip state to be maintained while rendering these mode pins inactive. Clock Enable (active low, internal pull-up) A logical LOW input to this pin enables CLKOUT. CLKEN* should be hardwired to ground to enable CLKOUT. Otherwise, CLKEN* should be left unconnected or connected to VDD. Clock Output This pin defaults to 14.31818 MHz upon power-up. Further toggling of the CLKEN* pin causes CLKOUT to output other internal test clocks. When disabled (i.e., CLKEN*=1), this output is a logic LOW. Setting the PD* pin low also causes CLKOUT to be logic LOW. Digital Supply Voltage These pins supply the 5V power to the digital section of CH7001C. For information on proper supply decoupling, please refer to Application Note AN-11. Digital Ground These pins provide the ground reference for the digital section of CH7001C, and MUST be connected to the system ground to prevent latchup. For information on proper supply decoupling, please refer to Application Note AN-11. Anti-flicker Mode Select Pins These two pins are used to select one of four possible anti-flicker vertical filter modes. Crystal Input 2 A 14.31818 MHz parallel resonance ( 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. Crystal Output or External FREF Input 2 A 14.31818 MHz ( 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative.
2, 4, 44
In
G, R, B
3, 38, 43
Power
AVDD
6
In
STROBE
7
In
CLKEN*
8
Out
CLKOUT
9, 13, 32
Power
DVDD
10, 14, 31
Power
DGND
11, 12
In
MS0, MS1
15
In
XI
16
In
XO/FIN
Note:
1 The Typical Connection Diagram (Figure 4 on page 6) shows the VGA input configured for applications that do not require RGB buffering before the monitor. In this configuration, 75 input termination must be guaranteed either by termination by the monitor connection, by discrete 75 resistors on the PCB, or by a dummy 75 termination connector. The total RGB trace on the PCB must be kept as short as possible to avoid cable reflection problems. For further information, request a copy of Application Note AN-11, "PC Board Layout Considerations for CH7001C. " 2 Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the tuning capacitor should be obtained from the crystal manufacturer. For further information, request a copy of Application Note AN-19, "Tuning Clock Outputs. "
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CHRONTEL
Table 1 * Pin Description (continued)
Pin
17, 37
CH7001C
Type
In
Symbol
PDI, PD0
Description
Power Down Inputs (active low, internal pull-up) Asserting these signals place CH7001C into different power-down states. (Refer to section on Power Management). Note: Use of these pins is optional. Leaving these two pins floating will maintain normal operating mode. DAC Power Supply These pins supply power to CH7001C's internal DACs. Please refer to Application Note AN-11 for information on proper supply decoupling. Reference Resistor A 330 resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin. DAC Ground These pins provide the ground reference for CH7001C's internal DACs. For information on proper supply decoupling, please refer to Application Note AN-11. Luminance Output A 75 termination resistor with short traces should be attached between Y and ground for optimum performance. An optional low pass filter circuit, shown in Figure 3 on page 5, may be used as an alternative to the ferrite bead shown in Figure 4 on page 6. Composite Output A 75 termination resistor with short traces should be attached between CVBS and ground for optimum performance. An optional low pass filter circuit shown in Figure 3 on page 5, may be used as an alternative to the ferrite bead shown in Figure 4 on page 6. Chrominance Output A 75 termination resistor with short traces should be attached between C and ground for optimum performance. An optional low pass filter circuit shown in Figure 3 on page 5, may be used as an alternative to the ferrite bead shown on Figure 4 on page 6. Up Position Control (active low, internal pull-up) UP allows the screen display position to be moved up incrementally for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. UP may be connected directly to the power supply or ground. Down Position Control (active low, internal pull-up) DOWN allows the screen display position to be moved down incrementally for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. DOWN may be connected directly to the power supply or ground. Left Position Control (active low, internal pull-up) LEFT allows the screen display position to be moved to the left incrementally for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. LEFT may be connected directly to the power supply or ground. Right Position Control (active low, internal pull-up) RIGHT allows the screen display position to be moved to the right incrementally for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. RIGHT may be connected directly to the power supply or ground. NTSC/PAL Mode Select Input (internal pull-up) A logical HIGH input NTSC/PAL* pin selects NTSC operation. A logical LOW input to NTSC/PAL* selects PAL operation. NTSC/PAL* accepts CMOS logic level inputs and may be connected directly to the power supply or ground.
18, 25
Power
VDD
19
In
RSET
20, 24
Power
GND
21
Out
Y
22
Out
CVBS
23
Out
C
26
In
UP
27
In
DOWN
28
In
LEFT
29
In
RIGHT
30
In
NTSC / PAL*
4
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CHRONTEL
Table 1 * Pin Description (continued)
Pin Type Symbol Description
CH7001C
33
In
UNDERSCAN
34
In
V
35
In
H
36
--
TEST*
39
In
VREF2
41
In
VREF1
Underscan Enable Pin (active high, internal pull-up) A logical HIGH input to UNDERSCAN results to an output screen that has approximately 12.5% horizontal underscan. This pin may be connected directly to the power supply or ground. Vertical Sync Input This pin accepts the vertical sync output from the VGA card. The capacitive loading on this pin should kept to a minimum. Horizontal Sync Input This pin accepts the horizontal sync output from the VGA card. The capacitive loading on this pin should kept to a minimum. Please refer to Application Note 11 "PC Board Layout Considerations for CH7001C." Test Pin (active low, internal pull-up) Connect a capacitor in the range of 2.2uF - 4.7uF from this pin to GND to ensure proper functionality of the UNDERSCAN/ OVERSCAN feature. Internal Voltage Reference VREF2 provides a typical 2.5V reference that is used as an internal bias to the ADCs. A 0.1 F decoupling capacitor should be connected between VREF2 and ground. ADC Voltage Reference Input / Output VREF1 provides a typical 1.235V reference that sets the RGB input full scale at 0.75V. A 0.1 F decoupling capacitor should be connected between VREF1 and ground. VREF1 may also be forced by external reference.
Optional Output Filter
47pF
1.2uH Y,C, CVBS 150pF
1.2uH OUTPUT 270pF
1
75 Ohms
Figure 3: Optional Output Filter
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CHRONTEL
Ferrite Bead +5V Ferrite Bead Ferrite Bead
CH7001C
0.1uF 0.1uF 10uF +
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
3 AVDD 35 7404 7404 34 4 R 2 44 B 75 Ohms 75 Ohms 75 Ohms G H V
38 AVDD
43 AVDD
18 VDD
25 VDD
9 DVDD
13 DVDD
32 DVDD 41 VREF1 0.1uF 39 VREF2 0.1uF 8 CLKOUT Ferrite Bead
VGA Card
21 Y 26
To MONITOR or TERMINATION RESISTORS
75 Ohms UP 23 C Ferrite Bead
Switch 27 DOWN 28 Switch LEFT
CH7001C
(PLCC pinout)
22
75 Ohms
29 RIGHT 12, 11 MS [1:0] 33 UNDERSCAN 30 NTSC/PAL* 7
Ferrite Bead
CVBS 75 Ohms
(1) 37,17
CLKEN* PD [0:1] 6 STROBE 36 TEST* 19 330 Ohms AGND 1 5 40 42 GND 20 24 DGND 10 14 31
2.2uF-4.7uF (2) 16
RSET XO/FIN
14.31818 MHz
15
XI
Figure 4: CH7001C Typical Connection Diagram
Note: 1 If the CLKOUT signal is not used, either connect CLKEN* to VDD, or leave it unconnected. Note: 2 An external pull-up resistor should not be connected to the TEST* pin.
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COMPOSITE CONNECTOR
S-VIDEO CONNECTOR
CHRONTEL
General Description
CH7001C
The CH7001C is a fully integrated solution for converting analog RGB and synchronization signals from a standard VGA source into high-quality NTSC or PAL video signals. All essential circuitry for this conversion (memory, memory control, PLL, ADC, DAC, digital filters, digital NTSC/PAL encoder) are present in this IC. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the highquality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing. CH7001C is ideal for stand-alone VGA to NTSC/PAL applications, where a minimum of discrete support components (passive components, 14.31818 MHz crystal) are required for full operation. The CH7001C easily integrates into notebook computers and PC add-on graphics cards.
Functional Description
The analog RGB inputs are digitized on a pixel-by-pixel basis by three 8-bit video A/D converters. The digitized RGB inputs are fed to a block where scan-rate conversion and programmable 3-line vertical filtering are performed. The vertical filter eliminates flicker at the output, while the scan-rate converter transforms the VGA horizontal scanrate to either NTSC or PAL scan-rates. The digitized RGB inputs are encoded into luminance (Y) and color-difference (U,V) signals through the color space converter. The resulting YUV signals are filtered through digital filters to minimize aliasing problems (the frequency response is shown in Figure 5 on page 8). The digital encoder receives the filtered signals and transforms them to composite and S-video outputs, which are converted by the three 8-bit DACs into analog outputs. Highquality video is ensured by using 24 bits per pixel processing throughout the entire signal path.
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CHRONTEL
General Description (continued)
Figure 5: U,V, and Y Filter Response CH7001C Detailed Frequency Response -0 -2 -4
dB
CH7001C
Y_SV Y_CV UV
-6
-8
-10 0 1 2 3
Freq (MHz)
4
5
6
CH7001C Frequency Response -0 -10 -20
dB
-30
-40
-50 0 1 2 3 4 5 6 7 8 9 10 11 12
Freq (MHz)
8
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CHRONTEL
General Description (continued)
Clock Generation and Video Timing
CH7001C
All clock signals of the CH7001C are generated from the VGA synchronization inputs by a low-jitter, PLL circuit. The VGA input and sync timing are illustrated in Figures 6 and 7 below. The VGA pixel clock is generated internally, using the VGA horizontal sync signal, and is used for sampling the RGB inputs pixel-by-pixel, which aids in preventing aliasing artifacts. All synchronization and color burst envelope pulses are internally generated using only the timing signals provided by the VGA synchronization inputs.
31.78 s
H
25.42 s
R,G,B DATA
3.81 s
ACTIVE VIDEO
1.91 s 0.64 s
Note: The timing diagram shown is for 640 x 480, 60 Hz VGA mode
Figure 6: Typical VGA Input Timing
31.78 s
H
63.56 s
V*
(ACTIVE LOW)
Figure 7: VGA Horizontal and Vertical Sync Timing
Internal Voltage Reference
The on-chip generated ADC voltage references are brought out to pins VREF1 and VREF2 for decoupling purposes. VREF1 and VREF2 should each have a 0.1 F decoupling capacitor between each pin and ground. VREF2 provides a typical 2.5V reference, used for setting the internal bias to the ADCs, and VREF1 provides a typical 1.235V reference, used for setting the RGB input full scale at 0.75V. VREF1 can be forced by an external voltage reference in order to accommodate different RGB input ranges. An additional on-chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a reference resistor at pin RSET, sets the output ranges of the DACs.
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General Description (continued)
Strobing
CH7001C
The CH7001C programmable pins (MS[1:0], UNDERSCAN, NTSC/PAL*, LEFT, RIGHT, UP, and DOWN) may be connected to shared signal lines and then strobed in using the STROBE pin. By asserting the STROBE pin high, the state of the programmable pins is internally sampled during the STROBE signal's high-to-low transition. A logical low input to the STROBE pin allows the chip state to be maintained, while rendering the programmable pins inactive.
Power Management
The CH7001C supports four operating states including Normal (On), Power Down, S-Video Off, and Composite Off) in order to provide optimal power consumption for the application involved. Using pins PD0 and PD1, the CH7001C ay be placed in either Normal state or any of the three power managed states as listed below: PD1 1 0 1 0 PD0 1 1 0 0 Operating State Normal (On) Power Down S-Video Off Composite Off Functional Description All functions and pins are active (default state with inputs floating.) Most pins and cicruitry are disabled. This reduces power to only 1% of normal operating power. Power is shut off to the unused DACs associated with Y and C outputs. This reduces power to 81% of normal operating power. Power is shut off to the unused DAC associated with CVBS output. This reduces power to 89% of normal operating power.
Color Burst Accuracy*
The CH7001C employs a proprietary technique for generating the color sub-carrier frequency. This method allows the sub-carrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the accuracy of the sub-carrier frequency independent of the sampling rate. As a result, the CH7001C is compatible with any VGA card, since the CH7001C sub-carrier frequency is not dependent on the pixel rates of VGA card manufacturers. This feature is a significant benefit, since even a 0.01% sub-carrier frequency variation may be enough to cause some television monitors to lose color lock.
10
*Patent number 5,874,846
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CHRONTEL
Programmability
CH7001C
All operational modes of the CH7001C are accessed directly through the package pins, making the CH7001C programmable without the use of an additional microcontroller. Some of the programmable features are: horizontal overscan/underscan control, NTSC or PAL operation, selectable anti-flicker filter modes, and adjustable horizontal and vertical display positioning capabilities.
Horizontal Overscan/Underscan
Horizontal underscan mode is enabled via the UNDERSCAN pin. By setting this pin high, the resulting output screen experiences a 12.5% horizontal underscan. The CH7001C also implements an overscan/underscan mode that is controllable through the PC. Software control is available only when the underscan input is inactive (i.e., UNDERSCAN = 0) and is accomplished by programming the length (in VGA line periods) of the vertical sync pulse. When the CH7001C detects the vertical sync pulse as having fewer than eight VGA line periods, the device operates in overscan mode; when it detects the vertical sync pulse as having more than eight VGA line periods, it operates in underscan mode. The CH7001C determines the number of VGA line periods through an internal circuitry that continuously analyzes the width of the VGA vertical sync input. Software control is overridden if the underscan input is set high.
NTSC or PAL Operation
Composite and S-video outputs are supported in either NTSC or PAL format, as shown in Figures 8 through 10. These outputs can be conveniently switched to either format via the NTSC/PAL* pin. If the NTSC/PAL* pin is set low, PAL output format is selected. If the NTSC/PAL* is set high, NTSC output format is selected. See Figures 11 through 16 on pages 14 through 16 for illustrations of the composite and S-video output waveforms.
A
B
C
D
E
F
G
H
Figure 8: NTSC / PAL Composite Output
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CHRONTEL
General Description (continued)
Table 2 * NTSC/PAL Composite Output Timing Parameters (in S)
Symbol A B C D E F G H NTSC OVERSCAN 1.35 4.69 0.64 2.66 1.47 2.38 50.51 0.00 UNDERSCAN 1.20 4.70 0.57 2.37 1.31 5.10 45.19 3.12 OVERSCAN 1.35 4.69 0.56 2.39 1.83 2.37 50.51 0.00 PAL
CH7001C
Description
Front Porch Horizontal Sync Breezeway Color Burst Back Porch Black Active Video Black
UNDERSCAN 1.20 4.70 0.49 2.12 1.63 5.11 45.19 3.12
START OF VSYNC ANALOG FIELD 1
520
521
522
523
524
525
1
2
3
4
5
6
7
8
9
ANALOG FIELD 2
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
LINE RATE = HALF THE VGA LINE RATE IN MODES 11 & 12 (640 x 480) FIELD RATE = VGA VERTICAL REFRESH RATE IN MODES 11 & 12 (640 x 480)
Figure 9: Interlaced NTSC Video Timing
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CHRONTEL
General Description (continued)
CH7001C
START OF VSYNC ANALOG FIELD 1
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
10
ANALOG FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
ANALOG FIELD 3
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
10
ANALOG FIELD 4
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
Figure 10: Interlaced PAL Video Timing
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CHRONTEL
CH7001C
MAGENTA
YELLOW
GREEN
Color / Level White Yellow Cyan Green Magenta Red Blue Black Blank
mA 24.60 27.48 22.85 25.41 19.85 22.08 18.11 20.01 15.23 16.99 13.49 14.93 10.49 11.59 8.74 9.69 8.26 7.49
V COLOR BARS : 0.922 1.030 0.857 0.953 0.745 0.828 0.679 0.750 0.571 0.637 0.506 0.560 0.393 0.435 0.327 0.363 0.281 0.310
Sync
0.50 0.640
0.019 0.024
Note: Note:
100% amplitude, 100% saturation color bars are shown VREF1 = 1.235V, RSET = 330, 75 doubly terminated load.
Figure 11: NTSC Y (Luminance) Output Waveform
MAGENTA
YELLOW
GREEN
Color / Level White Yellow Cyan Green Magenta Red Blue Black Blank
mA 26.05 24.60 24.00 22.85 20.67 19.85 18.59 18.11 15.57 15.23 13.52 13.49 10.19 10.49 8.74 7.49 8.26
V 0.977 0.922 0.900 0.857 0.775 0.745 0.697 0.679 0.584 0.571 0.507 0.506 0.393 0.382 0.327 0.281 0.310 COLOR BARS :
Sync
0.50 0.640
0.019 0.024
Note: Note:
100% amplitude, 100% saturation color bars are shown VREF1 = 1.235V, RSET = 330, 75 doubly terminated load.
Figure 12: PAL Y (Luminance) Video Output Waveform
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BLACK
WHITE
CYAN
BLUE
RED
BLACK
WHITE
CYAN
BLUE
RED
CHRONTEL
General Description (continued)
CH7001C
MAGENTA
YELLOW
GREEN
Color / Level
mA mA
VV
COLOR BARS :
Cyan / Red 22.60 0.848 26.51/26.66 0.994/1.000 Green / Magenta 25.89/25.89 0.971/0.971 21.85 0.819 Yellow / Blue 19.61 0.735 23.39/23.39 0.877/0.877
Peak Burst Blank Peak Burst
15.98 19.34 12.49 15.59
11.85 8.99
0.599 0.725 0.468 0.585
0.444 0.337
3.579545 MHz Color Burst (9 cycles) Yellow / Blue Green / Magenta Cyan / Red 5.37 7.8/7.8 0.201 0.292/0.292
5.3/5.3 0.199/0.199 3.12 0.117 2.37 0.089 4.68/4.52 0.175/0.170
Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 VREF1 = 1.235V, RSET = 330, 75 doubly terminated load.
Figure 13: NTSC C (Chrominance) Video Output Waveform
MAGENTA
YELLOW
GREEN
Color / Level Cyan / Red Green / Magenta Yellow / Blue
mA
VV
COLOR BARS :
0.994/1.000 26.51/26.66 0.848 22.60 25.89/25.89 0.819 0.971/0.971 21.85 23.39/23.39 0.735 0.877/0.877 19.61
Peak Burst Blank Peak Burst
16.23 19.34 12.49 15.59
11.85 8.74
0.609 0.725 0.468 0.585
0.444 0.328
4.433619 MHz Color Burst (10 cycles) Yellow / Blue Green / Magenta Cyan / Red 5.37 7.8/7.8 0.201 0.292/0.292
5.3/5.3 0.117 3.12 0.199/0.199 4.68/4.52 0.089 2.37 0.175/0.170
Note: 1 100% amplitude, 100% saturation color bars are shown
Figure 14: PAL C (Chrominance) Video Output Waveform
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BLACK
WHITE
CYAN
BLUE
RED
BLACK
WHITE
CYAN
BLUE
RED
15
CHRONTEL
General Description (continued)
CH7001C
MAGENTA
YELLOW
GREEN
WHITE
CYAN
Color / Level Peak Chroma W ite h
mA 33.89 33.23 27.37 27.47
V 1.271 1.246 1.026 1.030
COLOR BARS :
3.579545 MHz Color Burst (9 Cycles) Peak Burst B lack B lank Peak Burst 12.00 12.03 9.68 9.62 8.27 8.16 4.32 4.53 0.450 0.451 0.363 0.360 0.310 0.306 0.162 0.170
Sync
0.50 0.640
0.019 0.024
Note: VREF1=1.235V, RSET=330, 75, doubly terminated load.
Figure 15: Composite NTSC Video Output Waveform
MAGENTA
YELLOW
BLUE BLUE
RED
GREEN
WHITE
CYAN
Color / Level Peak Chroma W ite h
mA 31.81 33.89 26.05 27.37
V 1.271 1.193 1.026 0.977
COLOR BARS :
4.433619 MHz Color Burst (10 Cycles) Peak Burst B lank/Black Peak Burst 12.00 12.03 8.26 8.64 4.53 4.58 0.450 0.451 0.310 0.324 0.171 0.170
Sync
0.643 0.50
0.019 0.024
Note: VREF1=1.235V, RSET=330W, 75W, doubly terminated load.
Figure 16: Composite PAL Video Output Waveform
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RED
BLACK
BLACK
CHRONTEL
General Description (continued)
Anti-Flicker Filter Modes
CH7001C
The CH7001C integrates a 3-line vertical filter circuitry to help eliminate the flicker associated with interlaced displays. The CH7001C provides four anti-flicker filter modes programmable via the anti-flicker mode select pins MS[1:0]. For a list of the filter modes available, please refer to Table 3 below.
Table 3 * Anti-Flicker Filter Modes
MS1 0 0 1 1 MS0 0 1 0 1 Filter Modes 0:1:0 averaging 1:3:1 averaging 1:2:1 averaging 1:1:1 averaging
Programmability
Display Position Control
UP, DOWN, LEFT, and RIGHT are dedicated inut pins controlling the NTSC or PAL display position. Upon power up, the internal position registers for a typical VGA input center the display on the television screen. With each toggle of any position pin to ground, the display will shift four pixels in the respective direction. For example, if the LEFT pin is toggled to ground once, the screen display will move four pixels to the left. Similarly, if the RIGHT pin is toggled to ground once, the screen display will move four pixels to the right. The shift of the display occurs during the low-to-high transition of the position pin. Toggling conflicting pins, such as the LEFT and RIGHT pins for example, simultaneously is not allowed. The minimum time required for the display position pins to be held low is 40 ns.Electrical Specifications
Table 4 * Absolute Maximum Ratings
Symbol Description VDD relative to GND Input voltage of all digital pins1 Analog output short circuit duration Ambient operating temperature Storage temperature Junction temperature Vapor phase soldering (one minute) Maximum Power dissipation Min - 0.5 GND - 0.5 - 55 - 65 Typ Max 7.0 VDD + 0.5 125 150 150 220 TBD Units V V Sec C C C C W
TSC TAMB TSTOR TJ TVPS PMAX
Indefinite
Note: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of device at these or any other conditions above those indicated under the normal operating conditions section of this specification is not recommended, Exposure to absolute maximum rating conditions for extended periods may affect relaibility. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup.
201-0000-028 Rev 3.0, 6/2/99
17
CHRONTEL
Table 5 * Recommended Operating Conditions
Symbol VDD AVDD DVDD TA RL VREF1 VREF2 Description DAC power supply voltage Analog supply voltage Digital supply voltage Ambient operating temperature Output load to DAC outputs ADC voltage reference input/output Internal voltage reference Min 4.75 Typ 5.00 5.00 5.00 25 37.5 1.235 2.5 Max 5.25
CH7001C
Units V
0 1.20
70 1.32
C V V
Table 6 * Electrical Characteristics (Operating Conditions: T
Symbol Description Video D/A resolution Full scale output current Video level error using external reference using internal reference VREF1 input current (VREF1 = 1.235V) Total Current Consumption (both S-video & composite outputs are On) Min 8
A
=0
- 70 C, VDD = 5V 5%)
Max 8 Unit Bits mA % % A mA
Typ 8 33.89
5 10 10 340
IREF1
Note:
As applied to Tables 4, 5, and 6, Recommended Operating Conditions are used as test conditions unless otherwise specified.
Table 7 * Digital Inputs / Outputs
Symbol VOH VOL VIH VIL IPU ILK CDIN CDOUT Description Output high voltage Output low voltage Input high voltage Input low voltage Input internal pull-up current Input leakage current Input capacitance Output capacitance Test Condition @ TA = 25 IOH = - 400 A IOL = 3.2 mA Min 2.4 2.0 GND - 0.5 5 -10 Typ Units V 0.4 V VDD + 0.5 V 0.8 V 25 A 10 A pF pF Max
f = 1 MHz, VIN = 2.4V
7 10
ORDERING INFORMATION
Part number CH7001C-V Package type PLCC Number of pins 44 Voltage supply 5V
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201-0000-028 Rev 3.0, 6/2/99

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